1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, in particular, to a method for fabricating a dynamic random access memory (DRAM) having memory cells each of which is composed of a transistor and a stacked type capacitor.
2. Description of the Related Art
As a semiconductor memory device of which information can be read and written at any desired timing, a dynamic random access memory (DRAM) is known. Generally, the DRAM is composed of a memory cell array and a peripheral circuit. The memory cell array stores a large amount of information. The peripheral circuit inputs/outputs signals from/to the outside of the DRAM.
In the conventional DRAM, one memory cell thereof is composed of one transistor and one capacitor. The capacitor stores information corresponding to the storage amount of electric charges can be generally classified as a planer type, a trench type, and a stacked type. In the planer type, the capacitor is formed on a front surface of the silicon substrate. In the trench type, a groove is formed in the silicon substrate. The side walls of the groove are used as a capacitor. In the stacked type, an electrode is disposed on the silicon substrate. The upper surface and the side surface of the electrode are used as a capacitor. In the stacked type capacitor, the storage electrode can be extended to a field oxide film, a gate electrode, or an upper portion of a digit line. Thus, the capacitance of the capacitor can be increased corresponding to the increase of the surface area of the capacitor.
As the integration and density of the DRAM are becoming high, the surface area of the storage electrode decreases. Since the storage electric charge amount is proportional to the storage electrode area, the storage charge capacitance that can satisfactorily withstand a soft error cannot be accomplished. Thus, in the conventional DRAMs, the stacked type capacitor is widely used.
To secure a particular amount of storage electric charge for the structure of which the integration and density of the DRAMs is further increased, a cylinder-shaped stacked type capacitor has been proposed. The conventional stacked type capacitor uses upper and side surfaces of the stacked electrode for securing a desired capacity, whereas the cylinder-shaped stacked type capacitor uses a bottom surface, an outer side surface, and an inner side surface. Thus, the surface area of the storage electrode of the cylinder-shaped stacked type capacitor is larger than that of the stacked type capacitor for the area of the inner side surface.
As such a prior art, a method for fabricating a semiconductor device has been proposed as JPA Hei 6-151749.
Next, with reference to FIGS. 1 to 8, the known method for fabricating a cylinder-shaped stacked type capacitor will be described.
As shown in FIG. 1, a device separating oxide film 2 composed of a silicon oxide film is formed at a predetermined region on a main front surface of a P type silicon substrate 1 by the LOCOS method for a thickness of 4000 angstroms. Thereafter, a gate oxide film 3 is formed by a heat oxidizing method or the like. A gate electrode 4 composed of a polycrystal silicon of which a large amount of arsenic (As) or phosphorus (P) has been doped is selectively formed on the gate oxide film 3. Thereafter, ions of arsenic (As) are injected into the oxide film 3. Thus, diffusion layers 5a, 5b, and 5c are formed as a cell transistor. Next, a first inter-layer insulation film 6 is formed of a silicon oxide film (SiO.sub.2) or a silicon nitride film (Si.sub.3 N.sub.4).
Thereafter, as shown in FIG. 2, a first contact hole 7 that extends to the diffusion layer 5b is formed. A polycrystal silicon of which a large amount of arsenic (As) or phosphorus (P) has been doped is deposited on the entire front surface of the resultant structure and then patterned in a predetermined shape, thereby to form a digit line 8. Then, a second inter-layer insulation film 9 is formed of a silicon oxide film (SiO.sub.2) or a silicon nitride film (Si.sub.3 N.sub.4).
Next, as shown in FIG. 3, a second contact hole 10 which extends to the diffusion layers 5a and 5c is formed. A polycrystal silicon film 11a of which a large amount of arsenic (As) or phosphorus (P) has been doped is formed on the entire front surface of the resultant structure by the CVD method for a thickness of 1500 to 4000 angstroms. Thereafter, an insulation film 12 composed of a silicon oxide film is formed on the entire front surface of the resultant structure by the CVD method for a thickness of 5000 to 10000 angstroms. The height of the side surface portion of the storage electrode of the capacitor is defined by the film 12 thickness of the insulation film 12. Thereafter, a photoresist is applied on the front surface of the insulation film 12 and then patterned in a predetermined shape by a well known lithography method or the like, thereby to form a resist pattern 13.
Thereafter, as shown in FIG. 4, with a mask of the resist patter 13, the insulation film 12 is selectively removed by an etching process such as, for example, an anisotropic etching process. The resist pattern 13 is removed by ashing. With a mask of the patterned insulation film 12, a base portion 11b of the cylinder-shaped stacked type capacitor storage electrode is formed by for example the anisotropic etching method. Alternatively, with the resist pattern 13, the insulation film 12 is patterned. Just after that, with a mask of the resist pattern 13, the base portion 11b may be anisotropically etched out.
Next, as shown in FIG. 5, a polycrystal silicon film 14a of which a large amount of arsenic (As) or phosphorus (P) has been doped is formed on the entire front surface of the resultant structure for a thickness of 500 to 1000 angstroms by the CVD method. The polycrystal silicon film 14a is anisotropically etched out by the RIE (reactive ion etching) method. The RIE method can be performed with a parallel plate type RIE unit in the conditions that the radio frequency power is 0.3 Kw/cm.sup.2, the gas pressure is 150 mT, the flow rate of a chlorine (Cl.sub.2) gas is 50 sccm, the frequency is 13.56 MHz, and the etching time is 30 to 60 seconds.
Thereafter, the insulation film 12 is etched out for a predetermined thickness by a wet etching method using hydrogen fluoride, for example, so as to expose an edge portion of a side wall portion 14b. By anisotropically etching out the polycrystal silicon film 14a, a side wall portion 14b is formed in a shape as shown a in FIGS. 6A and 6B. FIG. 6B is an enlargement view showing a portion X of FIG. 6A.
In this state, the edge portion of the side wall portion 14b is sharply formed as illustrated in FIG. 6A. When a capacitor is formed on the side wall portion 14b, an electric field concentrates at the sharp portion. Thus, the service life of the capacitance insulation film decreases.
To solve this problem, the following process is performed. As shown in FIG. 7, the edge potion of the side wall portion 14b is spatter etched out with an inert gas such as argon (Ar) gas. For example, the spatter etching process is performed with the parallel plate type RIE unit in the conditions that the radio frequency power is in the range from 0.2 to 1.9 kW/cm.sup.2, the gas pressure is 30 mT or less the flow rate of argon (Ar) gas is in the range from 20 to 50 sccm, the frequency is 13.56 MHz or less, and the spatter etching time is in the range from 1 minute to 3 minutes. In the spatter etching process with an inert gas, since silicon crystal is physically etched out, the protruded portion is first etched out.
In the state shown in FIG. 6A, the side wall portion 14b is etched out by the spatter etching method. Thereafter, the insulation film 12 is completely removed by the wet etching method using hydrogen fluoride. Finally, a side wall portion 14c in a shape shown in FIGS. 8A and 8B is obtained. FIG. 8B is an enlargement view showing a portion Y of FIG. 8A.
Thus, the storage electrode of the cylinder-shaped stacked type capacitor that does not have a sharp edge portion of the side wall portion 14c is obtained.
As described above, the edge of the side wall portion 14b of the storage electrode of the cylinder-shaped stacked type capacitor shown in FIGS. 6A and 6B is sharply formed. When a capacitor is formed on the storage electrode, since the electric field concentrates at the edge portion of the side wall portion 14b, the service life of the capacitor insulation film decreases. In addition, when a capacitor insulation film is formed or when an opposite electrode is formed, the edge portion of the side wall portion 14b is broken. Thus, the yield of the final product may deteriorate. Consequently, a step for preventing the edge portion of the side wall portion 14b of the cylinder-shaped stacked type capacitor from being sharply formed should be added.
According to the related art reference, to prevent the edge portion of the side wall portion 14b form being sharply formed, after the anisotropic etching process of the polycrystal silicon film 14a is anisotropically etched out by the RIE method shown in FIG. 5, a step for wet-etching the insulation film 12 for a predetermined thickness and a step for spatter-etching the edge portion of the side wall portion 14b are required. Thus, the number of fabrication steps adversely increase.